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Progress on the front-end module design for NνDEx-100 experiment

Our research paper Prototype Design of the Readout System for NνDEx-100 Experiment has been published on the journal of IEEE Transactions on Nuclear Science. The link is 10.1109/TNS.2024.3471570.

This paper introduces the development of a 19-sensor front-end module, along with its functionality, performance testing, and tracking capability in conjunction with a Time Projection Chamber (TPC). This work is part of the ongoing R&D efforts for the readout and DAQ system of the NνDEx-100 experiment.

This work was supported in part by the National Key Research and Development Program of China (Grant No. 2022YFA1604703), and in part by the National Natural Science Foundation of China (Grant No. 12375189 and Grant No. 12105110).

我们的研究工作在 IEEE Transactions on Nuclear Science 发表。该论文介绍了19传感器前端模块的开发、功能与性能测试，以及与时间投影室（TPC）一起对粒子径迹的测量能力。该工作是NνDEx-100实验读出与数据采集系统研发的一部分。

该工作得到了国家重点研发计划课题（基金号2022YFA1604703）与国家自然科学基金项目（基金号12375189与12105110）的支持。

Progress on the digital-to-time converter research

Our research paper High precision low jitter pulse generator implemented with FPGA transceiver has been published on the journal of Measurement. The link is 10.1016/j.measurement.2024.114657.

In this paper, a new method for DTC design based on the FPGA transceiver is proposed and demonstrated. High precision about 1 picosecond is achieved. The jitter is obviously much lower compared to other FPGA based design.

This work was supported in part by the National Natural Science Foundation of China (Grant No. 12375189), and in part by the National Key Research and Development Program of China (Grant No. 2022YFA1604703). Meanwhile, this new method has been authorize a patent of invention in China.

我们的研究工作在 Measurement 期刊上发表。该论文中，一种新型基于FPGA高速收发器的数字时钟转换器（DTC）设计方法被提出并得到部署与验证。该方案达到了皮秒左右的高分辨，且其晃动明显低于其他基于FPGA的设计。

该工作得到了国家自然科学基金项目（基金号12375189）与国家重点研发计划课题（基金号2022YFA1604703）的支持。同时，基于该新方法的中国发明专利已经得到授权。

Progress on the sensor R&D for NνDEx experiment

Our research paper Performance of a novel charge sensor on the ion detection for the development of a high-pressure avalancheless ion TPC has been published on the journal of Journal of Instrumentation. The link is 10.1088/1748-0221/19/04/C04004.

In this paper, performance of the sensor for NνDEx experiment is presented. The mobility of negative ions in air and SF6 gases are measured. The study demonstrates that the sensor chip could be used for the ion detection.

This work was supported in part by the National Natural Science Foundation of China (Grant No. 12105110), and in part by the National Key Research and Development Program of China (Grant No. 2022YFA1604703).

我们的研究工作在 Journal of Instrumentation 发表。该论文展示了NνDEx实验传感器的性能。空气与六氟化硫气体中负离子的得到了测量。研究表明该传感器能用于离子电荷的测量。

该工作得到了国家自然科学基金项目（基金号12105110）与国家重点研发计划课题（基金号2022YFA1604703）的支持。

Progress on the readout and DAQ system R&D for NνDEx experiment

Our research paper Design and Demonstration of Digital Readout Chain in NνDEx Experiment has been published on the journal of IEEE Transactions on Nuclear Science. The link is 10.1109/TNS.2023.3319231.

In this paper, development and demonstration of the digital readout chain, including the front-end digital ASIC array, the data aggregation module, and the back-end PCIe card are introduced. It is the R&D of readout and DAQ systm for the NνDEx experiment.

This work was supported in part by the National Key Research and Development Program of China (Grant No. 2022YFA1604703), and in part by the National Natural Science Foundation of China (Grant No. 12075099).

我们的研究工作在 IEEE Transactions on Nuclear Science 发表。该论文介绍了NνDEx实验读出与数据获取系统的预研进展，具体包含了前端数字芯片阵列、数据汇总模块以及后端PCIe板卡的原型设计与集成验证。

该工作得到了国家重点研发计划课题（基金号2022YFA1604703）与国家自然科学基金项目（基金号12075099）的支持。

Progress on the FPGA based phase measurement system

Our research paper A high precision phase measurement system implemented in FPGA with phase interpolator has been published on the journal of Review of Scientific Instruments. The link is 10.1063/5.0078340.

In this work, the phase interpolator in Xilinx transceiver is used to generate a slight frequency difference for the DDMTD. The accuracy is guarrantted partly by the high quality integrated dedicated PLL inside the transceiver. An averaging measurement method is used to improve the linearity. Results are reported in this paper.

In 2024, this new method and system has been authorize a patent of invention in China.

我们的研究工作在 Review of Scientific Instruments 发表。该论文介绍了基于Xilinx FPGA高速收发器内部相位内插模块产生微小频率差从而实现DDMTD的方法。收发器内部高质量的PLL能有效提升系统测量精度。此外，本文提出了一种通过可控平均测量来消除内插模块的非线性的方法。

基于该新方法及系统设计的中国发明专利已经在2024年得到授权。